Designing phase logic using aliasing

You can create phase logic that uses aliasing by creating your logic at the phase class level and referencing the unit aliases instead of specific units in your expressions. The expression will still verify if the syntax is correct. For example, you can write an expression for a transition to wait on a transfer from one tank before proceeding to the next step (which could be a generic agitation step).

'//#INLET_A#/DC1/SP_D' = '//#VALVE_1#/CV:CLOSE' AND '//#TANK_A#/LP1/OUT' <= 0

(Where INLET_A, VALVE_1 and TANK_A are aliases.)

Note:

You can download phases that use references. The references are resolved at runtime based on the unit's phase table and the phase's valid aliases.

Create the phase class and write the logic. Assign the phase class to a unit class. When the unit class is instantiated in an area (and assigned to a process cell), a unit module is created with the unit phases already configured. When the phase is run, the unit used depends either on what is available or what the operator chooses (if you write that option into your logic).