Trap the first active interlock condition

Trapping and resetting the first active interlock condition are applicable only to interlock conditions.

The DCC block traps the active interlock condition when all the following conditions are True:

I_OUT_INT is non-zero (there is at least one condition active or latched);
ARM_TRAP is True (the trap mechanism is armed);
CMD_IN_D is not equal to I_OUT when I_OUT is not equal to 255 or CMD_IN_D is less than 10 when I_OUT=255 (the device to interlock is in a different state CMD_IN_D than the DCC block interlock state calculated I_OUT).

Note

When CMD_IN_D status is bad, the I_FIRST_OUT trap occurs immediately when the first two conditions are satisfied.

Note

If the trap mechanism is required only when the EDC block is in a state different than the interlock state calculated by the DCC block, connect CMD_IN_D to the CMD_D parameter of the downstream EDC block. CMD_IN_D corresponds to the command provided by the EDC block. When CMD_IN_D is greater or equal to 10, the state is passive.

Table: CMD_IN_D values
Value	Named State
0	State 0
1	State 1
2	State 2
3	State 3
4	State 4
5	State 5
10	State 0 Passive
11	State 1 Passive
12	State 2 Passive
13	State 3 Passive
14	State 4 Passive
15	State 5 Passive

When the trap occurs, I_FIRST_OUT is the bit value of the highest priority condition (lowest condition number) that is currently active.

I_FIRST_OUT retains its value until I_FIRST_OUT resets or another condition that has a different interlock state (I_STATEn) and a higher priority becomes active. I_FIRST_OUT changes to the bit value of the newly active condition.

Note

To prevent updating the first out after the first trap that occurred since the last reset, even if CMD_IN_D is not equal to I_OUT, configure the expression of a CND block to DCC/I_FIRST_OUT = 0 and wire the OUT_D of the CND block to the input ARM_TRAP of the DCC block.