SIS function blocks > SIS I/O Blocks > Logic Solver Digital Valve Controller function block

Logic Solver Digital Valve Controller function block execution

Because the Logic Solver is a De-energized to Trip environment the normal operating value of the output is On (1) and the tripped value is Off (0).

To use the LSDVC block in a safety shutdown application, assign IO_OUT to a Logic Solver HART Two-state Output channel or LS CHARM connected to a Fisher Controls DVC6000ESD digital valve controller. Typically, the CAS_IN_D input of the LSDVC block would be wired from an EFFECT output of an upstream LSCEM block. Default LSDVC block behavior passes the value of CAS_IN_D to OUT_D. 

You can wire feedback from the DVC6000ESD to the RDBK_IN_D input parameter of the LSDVC block. This input would typically be wired from an LSDI function block representing a limit switch. The RDBK_IN_D value becomes the PV_D of the LSDVC block. If the configurable time CFM_TRIP_TIME expires before PV_D confirms the off state, the DO_ALERTS Failed to confirm after trip command becomes True. If RDBK_IN_D is not wired, PV_D has the same value as OUT_D, so confirmation is immediate.

Fault State Detection

The LSDVC block enters a fault state when any of three conditions is detected and a corresponding option has been selected for the detected condition. When the fault state is active, the block forces OUT_D to Off, sets the Fault State Active bit in BLOCK_ERR, and sets FAULT_STATE to Active. The FSTATE_OPTS options are selected by default and include:

FSTATE_TIMER is a writeable parameter. Be advised that writing to FSTATE_TIMER can cause the state of OUT_D to change depending on the value written.

Determining the value of OUT_D and writing the output value

The following figure is the state transition diagram for OUT_D_STATE. When OUT_D_STATE is Off or Off - Ready to Reset, the value of OUT_D is Off (0) and the Logic Solver channel or LS CHARM defined by IO_OUT is written to Off. When OUT_D_STATE is On, OUT_D is On and IO_OUT is written to On.

Figure: OUT_D_STATE Transition Diagram


Note

To require a manual reset to transition OUT_D to On (1), it is recommended that you configure this in an upstream LSCEM block, not the LSDVC block. The LSCEM block has a number of features that enhance the reset logic. The ability to require resets in the LSDVC block (using the REQUIRE_RESET parameter) is provided if you do not have voter and LSCEM blocks to implement shutdown logic.

If you set the LSDVC block's REQUIRE_RESET parameter to True, any transition of OUT_D to Off (0) causes OUT_D to remain Off until all of the following conditions are met:

RESET should be changed to True using a button on a faceplate or process display in the operator environment. The block changes RESET back to False. Do not expose RESET as an input on the block and wire to it. If you need to reset an LSDVC block from SIS module logic, use an LSCALC function block to do a conditional assignment to RESET.

When REQUIRE_RESET is False, OUT_D's value is based on the value of CAS_IN_D unless the fault state is active.

When OUT_D_STATE is Off or Off - Ready to Reset, the value of OUT_D is Off and the channel or LS CHARM on this Logic Solver defined by IO_OUT is written to Off. This results in the configured OFF_CURRENT value (0 or 4 mA) being sent to the Logic Solver's HART Two-state Output channel or LS CHARM defined in IO_OUT.

When OUT_D_STATE is On, OUT_D is On and the channel or LS CHARM is written to On. This results in 20 mA being sent to the Logic Solver's HART Two-state Output Channel or LS CHARM.

Determining the value of PV_D

PV_D normally gets its value from RDBK_IN_D. If the status of RDBK_IN_D is BadNotConnected, PV_D has the same value as OUT_D. Use the invert input option in the upstream LSDI function block if you are using a closed limit switch. You can manipulate PV_D to test an operator display or test the confirmation alarm condition by using simulation in the upstream input function block (simulation available when the Logic Solver is assigned to the ProfessionalPLUS workstation as a simulated Logic Solver).

Determining the value of DO_ALERTS

The DO_ALERTS parameter reports two alarm conditions set by the block (inactive = 0, active = 1):

Partial stroke testing

Perform partial stroke testing of a DVC6000ESD in one of the following ways:

Note

  Do not attempt to initiate consecutive partial stroke tests from the logic unless you verify that each test completes before initiating the next. Otherwise, the first test succeeds and subsequent tests fail or are denied until the first test completes. 

The partial stroke testing facility in the LSDVC block is in one of three states as indicated in the PST_STATE parameter, whose state transition diagram is shown in the following figure.

Figure: PST_STATE Transition Diagram


The partial stroke testing state is Idle when the block has not been configured to initiate tests periodically, that is, PST_PERIOD_TIME is zero hours, and the block is waiting for a manual test to be initiated by PST_START.

The state is Armed when PST_PERIOD_TIME is greater than zero and PST_NEXT_TIMER is timing down. A test starts when PST_NEXT_TIMER reaches zero (times out), or if prior to timing out, a manual test is started.

The state transitions to PST in Progress when a test is started from Idle or Armed. The block sends a request to the IO subsystem to initiate a partial stroke test. The block generates an event based on whether the test was successful, failed, or denied. The state then transitions to Armed or Idle based on the value of PST_PERIOD_TIME.

A partial stroke test can fail for a number of reasons:

When a partial stroke test fails, the block sets the PST_ALERTS Test failed. The alert remains set until the next time PST_STATE is PST in Progress.

The partial stroke test can be denied by the DVC6000ESD when it is in some modes of operation, for example, it is being calibrated or a test has been initiated from Valvelink, or the connected HART device does not support partial stroke testing. When a test is denied, the block sets the PST_ALERTS Test Denied, where it remains set until the next time PST_STATE is PST in Progress.

When PST_STATE is Armed or Idle, the block compares the elapsed time since the last successful test, PST_SINCE_TIMER, to the maximum allowed time between successful tests, PST_REQ_INTERVAL, and sets a the PST_ALERTS No successful test in the required interval if the time has been exceeded (unless the required interval is zero). PST_SINCE_TIMER is set to zero after a test succeeds. PST_SINCE_TIMER does not begin incrementing after an initial download of the Logic Solver until a successful test has occurred.

A transition can occur between Idle and Armed when PST_PERIOD_TIME is written in runtime, or on the first scan after a download if PST_PERIOD_TIME has changed. When the state is Idle, changing PST_PERIOD_TIME to a value greater than zero causes the state to change to Armed and PST_NEXT_TIMER to be initialized. When the state is Armed, writing PST_PERIOD_TIME to zero changes the state to Idle. When Armed, a greater than zero write to PST_PERIOD_TIME changes PST_NEXT_TIMER to the value written to PST_PERIOD_TIME if that value is less than the current value of PST_NEXT_TIMER. PST_NEXT_TIMER is decremented when the state is Armed.

When a download of the Logic Solver occurs where there is an existing configuration running, the current state and timer values are copied from running LSDVC blocks to retain the values.

Event Generation

The LSDVC block generates an event record when any of the following conditions become active and the REPORT_OPTS option Event records are not generated is not selected: